1. Field of the Invention
The present invention relates to a dynamic memory, and more specifically to a dynamic memory having an increased access speed and an increased cycle speed and a reduced chip area of a timing control circuit incorporated in a memory chip and a reduced power consumption of the memory chip.
2. Description of Related Art
Referring to FIGS. 4A and 4B, a circuit construction of a conventional DRAM (dynamic random access memory). FIG. 4A is a block diagram illustrating the construction of the conventional DRAM, and FIG. 4B is a circuit diagram illustrating a detailed circuit construction of one memory cell circuit set composed of a DRAM cell circuit and associated sense amplifier circuits, included in the conventional DRAM.
As shown in FIG. 4A, the conventional DRAM includes a plurality of memory cell circuit sets each of which includes a DRAM cell (memory cell) circuit 1 and associated SA (sense amplifier) circuits 2. The plurality of memory cell circuit sets are arranged in the form of an array. Each of the DRAM cell circuit 1 is associated with a word driver 3, and the SA circuits 2 associated to each DRAM cell circuit are associated with a SA (sense amplifier) driver 4, which is supplied with a SA (sense amplifier) enable signal SAE.
In common to all the memory cell circuit sets each composed of the DRAM cell circuit 1 and the associated sense amplifier circuits 2, a SA (sense amplifier) selection circuit 6, a DA (data amplifier) circuit 7 and a data input/output circuit 5 are provided. The DA circuit 7 receives a DA (data amplifier) control signal DAE, and the data input/output circuit 5 receives a write enable signal WE and a read enable signal RE.
Referring to FIG. 4B which is a detailed circuit diagram of the first memory cell circuit set of the DRAM cell circuit 1 and the associated sense amplifier circuits 2, the DRAM cell circuit 1 includes a plurality of word lines SWL (only two word lines SWL1 and SWL2 are shown for simplification of the drawing), and a plurality of pairs of bit lines BL and {overscore (BL)}. At each of intersections between the word lines and the bit lines, a DRAM memory cell 11 is located and connected to a corresponding word line and a corresponding bit line. One SA circuit 2 is provided for each bit line pair, and it is an ordinary practice in an integrated circuit layout that the SA circuits 2 are located at an upper side and at a lower side of the DRAM cell circuit 1, in symmetry to the DRAM cell circuit 1. In the drawing, however, a detailed circuit diagram of only the lower side SA circuits is shown for avoiding complication of the drawing.
The SA circuit 2 includes a sense amplifier 21 having a pair of (input/output) terminals connected to a corresponding pair of bit lines BL and {overscore (BL)}, a read switch 25 having a pair of input terminals connected to the corresponding pair of bit lines BL and {overscore (BL)} and a pair of output terminals connected to a pair of output terminals OL and {overscore (OL)}, a write switch 26 having a pair of input terminals connected to a pair of input terminals and {overscore (IL)} and a pair of output terminals connected to the corresponding pair of bit lines BL and {overscore (BL)}, and a precharge equalizer 27 for precharging and equalizing the corresponding pair of bit lines BL and {overscore (BL)}. The precharge equalizer 27 is connected to a half power supply voltage HVCC (=VCC/2) and controlled by a precharge equalize signal PDL. Each sense amplifier 21 is connected to a pair of sense amplifier power supply voltages SAN and SAP. Each read switch 25 is controlled by a corresponding read signal RSi (i=1 to 4), and each write switch 26 is controlled by a corresponding write switch WSi (i=1 to 4).
Referring to FIG. 5, there is shown a timing chart for illustrating an actual operation of the conventional DRAM shown in FIGS. 4A and 4B. Now, a reading operation will be described. First, one word line SWL (SWL1, SWL2, etc.) is selected, so that data is read out from each of the memory cells 11 connected to the selected word line, to a corresponding bit line pair. Then, the SA circuit is enabled by the SA enable signal SAE, so that the data is written back to the memory cell, and the data of the SA circuit selected by the read signal RS (RS1, RS2, RS3, RS4 etc.) by action of the SA selection circuit 6 is transferred to the DA circuit 7. The DA circuit 7 is enabled by the DA control signal DAE, so that the data is amplified again. The amplified data is outputted to the data input/output circuit 5, and finally, the data is outputted from the data input/output circuit 5 to a device external to the memory.
In the above mentioned operation, the read signal RS is required to be supplied after the signal on the bit line pair has sufficiently been amplified. However, since a capacitance and a resistance of the bit line pair are large, it is necessary to insert a time difference between the activation of the SA enable signal SAE and the inputting of the read signal RS.
Next, a writing operation will be described. Data supplied through the data input/output circuit 5 is amplified by the DA circuit 7 enabled by the DA control signal DAE, and transferred to the SA circuit selected by the write signal WS (WS1, WS2, WS3, WS4 etc.) by action of the SA selection circuit 6. Data is written into the DRAM cell 11 by forcibly rewriting the data in the SA circuit by the data supplied from the DA circuit 7. Accordingly, the operating sequence of the SA circuit and the DA circuit is required to be reversed from the data reading operation to the data writing operation, and therefore, the control circuit for operating the DRAM becomes complicated.
A first problem in the above mentioned conventional DRAM is that a high speed access cannot be obtained. The reason for this is that since the capacitance and the resistance of the bit line are large, it is necessary to insert a time difference between the activation of the SA enable signal SAE and the inputting of the read signal RS.
A second problem in the above mentioned conventional DRAM is that the timing control circuit for the reading/writing operation is complicated, with the result that the access speed, the chip area and the power consumption are inevitably increased. The reason for this is that, in the memory including the SA circuit and the DA circuit, the activation sequence of the SA circuit and the DA circuit is required to be changed from the data reading operation to the data writing operation.
Accordingly, it is an object of the present invention to provide a dynamic random access memory which has overcome the above mentioned problems of the conventional one.
Another object of the present invention is to speed up the data reading and writing operation in a dynamic random access memory, and to reduce the area of a timing control circuit incorporated in the dynamic random access memory and the power consumption of the dynamic random access memory, thereby to provide a high-speed, low power consumption, inexpensive dynamic random access memory.
The above and other objects of the present invention are achieved in accordance with the present invention by a dynamic memory including a first sense amplifier circuit directly connected to a bit line of a memory cell, a second sense amplifier directly connected to a data input/output circuit, a switching circuit connected between the first sense amplifier circuit and the second sense amplifier circuit, and a control means for controlling the switching circuit to separate the first sense amplifier circuit and the second sense amplifier circuit from each other after data is read out from the memory cell, so that the read-out data is amplified by the second sense amplifier circuit and outputted from the second sense amplifier circuit to an external of the memory.
Furthermore, the read-out data is amplified and written back to the memory cell by the first sense amplifier circuit. In a writing operation, the control means controls the switching circuit to interconnect the first sense amplifier circuit and the second sense amplifier circuit to each other, so that data to be written from an external is written into the memory cell through the first and second sense amplifier circuits.
Preferably, the control means is so configured to generate various control signals for the first and second sense amplifier circuits used in the reading operation, at the same timings as timings of various control signals for the first and second sense amplifier circuits used in the writing operation. In addition, in the writing operation, a predetermined logic level is written into only one of a pair of terminals of the first sense amplifier circuit. Furthermore, one second sense amplifier circuit is provided in common to a plurality of first sense amplifier circuits.
With the above mentioned arrangement, the first and second sense amplifier circuits are provided for the bit line connected to the memory cell, so that the sense amplifier used for the writing operation of the memory cell is separated from the sense amplifier used for the reading operation for outputting data from the memory cell to the external, with the result that a load on respective input/output terminals of the first and second sense amplifier circuits are reduced. Therefore, the high speed reading and writing become possible.
In addition, in the writing operation, the data supplied through the external is caused to pass through the second sense amplifier circuit and to be amplified by the first sense amplifier circuit so that the amplified data is written into the memory cell. As a result, the timings of various control signals for the first and second sense amplifier circuits can be made to be the same in both the reading operation and in the writing operation. Therefore, it is possible to reduce the area of the timing control circuits incorporated in the memory chip and the power consumption of the memory chip.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.